The present invention relates to feedback systems used in self-biasing phase-locked loops, and more particularly to self-biasing phase-locked loops employing VCO-matched bias generators, isolated charge pumps, and spread spectrum frequency output.
Phase-locked loop (PLL) systems are used extensively in analog and digital circuits. These systems typically include a phase frequency detector (PFD), charge pump and voltage controlled oscillator (VCO) connected in a feedback configuration. The VCO produces the output signal of the PLL, and the various components of the PLL cooperate to cause the output signal to tend toward and eventually lock on to a desired output frequency, which is based on a reference signal applied as an input to the PFD. For example, many PLL systems are configured to produce an output signal having the same frequency as the input signal, or having an output frequency which is a factor x/y of the input frequency.
The output signal tracks the desired output frequency through operation of a feedback mechanism, in which the output of the VCO is fed back to the PFD as a feedback signal via a feedback path. The phase frequency detector receives the reference signal and the feedback signal, and produces an error signal based on discrepancies between the actual phase and frequency of the output signal and the desired phase and frequency. The error signals from the PFD are applied to the charge pump, which in turn produces signals that control the oscillation frequency of the VCO.
Minimizing or reducing uncontrolled jitter in the output signal is an important design issue in PLL systems. Jitter is variation in the phase and/or frequency of the output signal when the system is aligned or very nearly aligned. Most PLL systems exhibit some amount of jitter in the output signal. Indeed, many PLL systems have what is known as a xe2x80x9cdead band,xe2x80x9d or a range of output alignments through which the system exerts little or no control over the output signal. This problem is addressed in some designs through phase frequency detectors configured to generate simultaneous canceling error signals when the system is in lock. Although this solution can reduce jitter, conventional implementations tend to introduce static phase offsets in the output signal, that is, an average phase discrepancy between the output signal and the desired phase.
In addition to the above problems, many existing PLL systems have other shortcomings which can have undesirable affects on the PLL output signal. For example, some systems suffer from undesired signal coupling between the various PLL components, which can lead to noise or jitter in the output signal. In other designs, the VCO and other PLL components are susceptible to voltage variations or noise coupled into the system from the voltage supply or other sources.
In addition, conventional phase-locked loops typically include components designed to operate under fixed or relatively fixed conditions. This can reduce the flexibility of the design, and constrain its use to a limited range of applications. For example, many PLL systems are designed for frequency multiplication by a predetermined scale factor, and are not easily modified for multiplication by other scale factors. In many cases, this inflexibility is the result of components that are designed to operate under fixed bias conditions.
The present invention provides a phase-locked loop configured to cause an output signal to tend toward a desired output frequency based on an applied reference signal. According to one aspect of the invention, the phase-locked loop includes a voltage controlled oscillator operatively coupled with a bias generator. The voltage controlled oscillator is configured to produce the output signal in response to a VCO current generated via application of a biasing signal from the bias generator. The VCO current produces a regulated VCO voltage within the voltage controlled oscillator. The bias generator is configured so that the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage.
According to another aspect of the present invention, the phase-locked loop includes a charge pump system having semiconductor components that correspond to only a portion of a voltage controlled oscillator associated with the loop. The semiconductor components are selected to provide the charge pump system with an effective impedance that is matched to an effective impedance of the voltage controlled oscillator. According to this aspect of the invention, the phase-locked loop further includes a bias generator configured to use the effective charge pump impedance to bias the charge pump system and thereby produce within the charge pump system a charge pump current of equal density to a VCO current used to drive the voltage controlled oscillator.
According to yet another aspect of the invention, the phase-locked loop includes a charge pump that is biased with a biasing signal applied to the charge pump via an isolated bias input path, to prevent undesired signal coupling between the charge pump and other components of the phase-locked loop.
According to further aspects of the invention, the phase-locked loop may be variously configured to employ charge pumps providing output to an isolated output path, and/or to provide an output signal exhibiting spread spectrum behavior.